The present invention disclosed herein relates to a photomask with an overlay mark and a method of fabricating a semiconductor using the photomask.
Semiconductor devices can be manufactured through deposition, ion implantation, photolithography, and etching steps. Theses steps may be repeated several tens to several hundreds of times to manufacture a semiconductor device. For example, a process of manufacturing a semiconductor device may include forming a device isolation pattern layer for isolating active regions from each other, forming gate patterns across the active regions, and forming plugs contacting the gate patterns. The device isolation pattern layer, the gate patterns, and the plugs may be respectively formed by deposition, photolithography, and etching steps.
Most modern semiconductor devices are constructed in three dimensions by stacking fine patterns of two-dimensional structures. Generally, fine patterns formed in the same process can be properly arranged in two dimensions since the fine patterns are formed using one photomask. If the fine patterns are formed by using different photomasks (e.g., gate patterns and plugs), however, proper alignment of the photomasks and the resulting layers is key to making a functioning three-dimensional structure.
In conventional practices, alignment marks or overlay marks formed in photomasks are used for the arrangement. It is difficult to properly arrange fine patterns at high accuracy of overlay using this method, however. The locations of alignment or overlay marks formed in the previous process are monitored during the photolithography processes. Conventional methods of measurement use the scattering or reflection characteristics of a light beam to measure whether the overlay patterns have been accurately placed. Such phenomena results from a difference between overlay marks and the surroundings.
One problem is that overlay marks formed together with a lower pattern may be deformed during the following processes such as etching, deposition, or chemical mechanical polishing (CMP). In this case, the overlay accuracy of the patterns cannot be precisely measured since the scattering or reflection characteristics of a light beam are affected by the deformation of the overlay marks.
An additional problem is that one alignment mark may not be proper for all purposes. It is known, for instance, that etching, deposition, and CMP processes affect the overlay accuracy of the patterns in different ways. For example, it is advantageous to use overlay marks with a smaller line width for a deposition or etching process. In contrast, it may be advantageous to use overlay marks with a larger line width for alignment during CMP processes.
In order to achieve a desired overlay accuracy, therefore, it is required that multiple overlay marks be formed with various line widths such that they can be used for monitoring various process conditions. That is, the number of overlay marks may be increased for obtain desired overlay accuracy. However, there is only a limited space available for such marks and increasing the number of overlay marks would result in a corresponding decrease in the areas used for testing and fabricating a chip, such as a test pattern and a chip region. That is, although overlay marks having various line widths are required to cope with various process conditions, the number of the overlay marks should be kept at a minimal level since the area of a wafer is limited.
Accordingly, the need remains for overlay marks of the type that improve accuracy of measurement under various process conditions while minimizing the area of the wafer dedicated to such overlay structures.